osdev-notes/Registers.md

x86 has a lot of curious registers. Their purposes and quirks are explored here.

General Purpose Registers

Used in normal operation of kernel space & user space programs.

64-bit	32-bit	16-bit	High 8	Low 8	Description
RAX	EAX	AX	AH	AL	Accumulator
RBX	EBX	BX	BH	BL	Base
RCX	ECX	CX	CH	CL	Counter
RDX	EDX	DX	DH	DL	Data
RSI	RSI	SI		SIL	Source
RDI	EDI	DI		DIL	Destination
RSP	ESP	SP		SPL	Stack Pointer
RBP	EBP	BP		BPL	Stack Base

Pointer Registers

Used infrequently by the kernel when performing context switches.

64-bit	32-bit	16-bit	Description
RIP	EIP	IP	Instruction Pointer

Segment Registers

Used more often when doing memory segmentation, as opposed to paging. Still required when doing paging, since you still need a GDT.

16-bit	Description
CS	Code Segment
DS	Data Segment
ES	Extra Segment
SS	Stack Segment
FS	General Purpose F Segment
GS	General Purpose G Segment

EFLAGS Register

A set of flags that are set or unset by the ALU to indicate the results of an operation.

Bit	Label	Description
0	CF	Carry Flag
2	PF	Parity Flag
4	AF	Auxiliary Flag
6	ZF	Zero Flag
7	SF	Sign Flag
8	TF	Trap Flag
9	IF	Interrupt Enable Flag
10	DF	Direction Flag
11	OF	Overflow Flag
12..=13	IOPL	IO Privilege Level
14	NT	Nested Task Flag
16	RF	Resume Flag
17	VM	Virtual 8086 Mode Flag
18	AC	Alignment Check
19	VIF	Virtual Interrupt Flag
20	VIP	Virtual Interrupt Pending
21	ID	CPUID Instruction Allowed

Control Registers

These special registers are set by the CPU and, on occasion, modified to change the behavior of certain instructions or tasks.

CR0

Bit	Label	Description
0	PE	Protected Mode Enable
1	MP	Monitor co-processor
2	EM	x87 FPU Emulation
3	TS	Task switched
4	ET	Extension type
5	NE	Numeric error
16	WP	Write protect
18	AM	Alignment mask
29	NW	Not-write through
30	CD	Cache disable
31	PG	Paging

CR2

Bit	Label	Description
0..=31	PFLA	Page Fault Linear Address

CR3

Bit	Label	Description	PAE	Long Mode
3	PWT	Page-level Write-Through	(Not used)	(Not used if bit 17 of CR4 is 1)
4	PCD	Page-level Cache Disable	(Not used)	(Not used if bit 17 of CR4 is 1)
12-31 (63)	PDBR	Page Directory Base Register	Base of PDPT	Base of PML4T/PML5T

CR4

Bit	Label	Description
0	VME	Virtual 8086 Mode Extensions
1	PVI	Protected-mode Virtual Interrupts
2	TSD	Time Stamp Disable
3	DE	Debugging Extensions
4	PSE	Page Size Extension
5	PAE	Physical Address Extension
6	MCE	Machine Check Exception
7	PGE	Page Global Enabled
8	PCE	Performance-Monitoring Counter enable
9	OSFXSR	Operating system support for FXSAVE and FXRSTOR instructions
10	OSXMMEXCPT	Operating System Support for Unmasked SIMD Floating-Point Exceptions
11	UMIP	User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)
12	LA57	57-bit linear addresses (if set, the processor uses 5-level paging otherwise it uses uses 4-level paging)
13	VMXE	Virtual Machine Extensions Enable
14	SMXE	Safer Mode Extensions Enable
16	FSGSBASE	Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE
17	PCIDE	PCID Enable
18	OSXSAVE	XSAVE and Processor Extended States Enable
20	SMEP	Supervisor Mode Execution Protection Enable
21	SMAP	Supervisor Mode Access Prevention Enable
22	PKE	Protection Key Enable
23	CET	Control-flow Enforcement Technology
24	PKS	Enable Protection Keys for Supervisor-Mode Pages

CR8

Bit	Label	Description
0-3	TPL	Task Priority Level