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Registers!

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August 2025-09-25 22:24:58 -04:00
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Physical & Virtual Memory.md
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Most processes are not permitted to directly access physical memory. Access is mediated transparently through the MMU (Memory Management Unit). Even the kernel's memory access is mediated through the MMU, so that it can account for all the allocated physical memory, and so that it doesn't overwrite its own address space. Most processes are not permitted to directly access physical memory. Access is mediated transparently through the MMU (Memory Management Unit). Even the kernel's memory access is mediated through the MMU, so that it can account for all the allocated physical memory, and so that it doesn't overwrite its own address space.
## Physical Memory ## Physical Memory
Physical memory on x86 is divided into "Page Frames". A Page Frame is a strictly physical concept. Physical memory on x86 is divided into "Page Frames":
- Strictly physical.
- Serves as the backing for a "Page", which is strictly virtual.
- All of physical memory is separated into a number of page frames.
- Can be either 4KiB, 2MiB, or 1GiB depending on the "level" of paging.
This is a useful abstraction, because pages must be aligned at a multiple of their size - for example, a 2MiB page must be aligned on a 2MiB boundary. In the simplest setup involving 2MiB pages, all of physical memory would be divided into 2MiB page frames for accounting.
## Virtual Memory & Pages
### 32-Bit Paging
32-Bit Paging involves two tables, or two "levels", that are traversed to determine the physical location of a logical address. The first table is the "Page Directory", and each entry in the page directory points to a "Page Table", which contains entries pointing to physical frames. In a sense, each entry in the page table is a page, in that it represents one physical page frame.
Both the page directory, and each page table, contains 1024 4-byte (32-bit) entries. Overall, the page directory is 4096KiB, and so is each page table.
In 32-bit paging mode, bits 12..=31 of the register CR3 indicate the address of the root page directory.
Each page directory entry looks like this:
| 31..=12 | 11..=8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ----------------------- | ------ | ---- | --- | --- | --- | --- | --- | --- | --- |
| Bits 31..=12 of address | AVL | PS=1 | AVL | A | PCD | PWT | U/S | R/W | P |
If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table.
| 31..=22 | 21 | 20..=13 | 12 | 11..=9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ----------------------- | ---- | ----------------------- | --- | ------ | --- | ---- | --- | --- | --- | --- | --- | --- | --- |
| Bits 31..=22 of address | RSVD | Bits 39..=32 of address | PAT | AVL | G | PS=0 | D | A | PCD | PWT | U/S | R/W | P |
If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table.
Here are the keys and their meanings:
- RSVD: Reserved - Must be set to 0, otherwise, will cause a page fault.
- P: Present - If this bit is 1, the page is in memory. If this bit is 0, accessing the page will throw a Page Fault.
- R/W: Read-Write - If this bit is 1, the page is writable. If this bit is 0, the page is read-only, and writing to it will Page Fault.
- U/S: User/Supervisor - If this bit is 1, the page is accessible by unprivileged code. If this bit is 0, it is only accessible to the kernel or supervisor.
- PWT: Page Write-Through - If this bit is 1, write-through caching is enabled, and changes to the cache are immediately written to physical memory. If this bit is 0, changes to the cache are only written when the cache is invalidated.
- PCD: Page Cache Disable - If this bit is set, the page will not be cached.
- A: Accessed - Set to 1 by the CPU if the Page Directory Entry was read by the CPU, as opposed to the address being obtained from the TLB.
- D: Dirty - Set to 1 if a page is written to.
- PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table.
- G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified.
- AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits.
#### Pages
A page is a virtual, contiguous segment of memory, which is backed by exactly one page frame. A page is defined by its entry in a page table, or page directory, each of which may contain up to 4096 pages.
#### Address Translation Example
If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address), the MMU would separate the address into three parts.
Address: `0xdeadbeef` / `0b11011110101011011011111011101111`
First 10 bits: `0b1101111010` / 890 - Page Directory Offset (Page Table)
Next 10 bits: `0b1011011011` / 731 - Page Table Offset (Page Table Entry)
Last 12 bits: `0b111011101111` / 3823 - Offset from start of page
So the MMU would search for the 3,823rd byte, of the 731st page, of the 890th page table.

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Registers.md Normal file
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x86 has a lot of curious registers. Their purposes and quirks are explored here.
## General Purpose Registers
Used in normal operation of kernel space & user space programs.
| 64-bit | 32-bit | 16-bit | High 8 | Low 8 | Description |
| ------ | ------ | ------ | ------ | ----- | ------------- |
| RAX | EAX | AX | AH | AL | Accumulator |
| RBX | EBX | BX | BH | BL | Base |
| RCX | ECX | CX | CH | CL | Counter |
| RDX | EDX | DX | DH | DL | Data |
| RSI | RSI | SI | | SIL | Source |
| RDI | EDI | DI | | DIL | Destination |
| RSP | ESP | SP | | SPL | Stack Pointer |
| RBP | EBP | BP | | BPL | Stack Base |
## Pointer Registers
Used infrequently by the kernel when performing context switches.
| 64-bit | 32-bit | 16-bit | Description |
| ------ | ------ | ------ | ------------------- |
| RIP | EIP | IP | Instruction Pointer |
## Segment Registers
Used more often when doing memory segmentation, as opposed to paging. Still required when doing paging, since you still need a GDT.
| 16-bit | Description |
| ------ | ------------------------- |
| CS | Code Segment |
| DS | Data Segment |
| ES | Extra Segment |
| SS | Stack Segment |
| FS | General Purpose F Segment |
| GS | General Purpose G Segment |
## EFLAGS Register
A set of flags that are set or unset by the ALU to indicate the results of an operation.
| Bit | Label | Description |
| ------- | ----- | ------------------------- |
| 0 | CF | Carry Flag |
| 2 | PF | Parity Flag |
| 4 | AF | Auxiliary Flag |
| 6 | ZF | Zero Flag |
| 7 | SF | Sign Flag |
| 8 | TF | Trap Flag |
| 9 | IF | Interrupt Enable Flag |
| 10 | DF | Direction Flag |
| 11 | OF | Overflow Flag |
| 12..=13 | IOPL | IO Privilege Level |
| 14 | NT | Nested Task Flag |
| 16 | RF | Resume Flag |
| 17 | VM | Virtual 8086 Mode Flag |
| 18 | AC | Alignment Check |
| 19 | VIF | Virtual Interrupt Flag |
| 20 | VIP | Virtual Interrupt Pending |
| 21 | ID | CPUID Instruction Allowed |
## Control Registers
These special registers are set by the CPU and, on occasion, modified to change the behavior of certain instructions or tasks.
### CR0
|Bit|Label|Description|
|---|---|---|
|0|PE|Protected Mode Enable|
|1|MP|Monitor co-processor|
|2|EM|x87 FPU Emulation|
|3|TS|Task switched|
|4|ET|Extension type|
|5|NE|Numeric error|
|16|WP|Write protect|
|18|AM|Alignment mask|
|29|NW|Not-write through|
|30|CD|Cache disable|
|31|PG|Paging|
### CR2
| Bit | Label | Description |
| ------ | ----- | ------------------------- |
| 0..=31 | PFLA | Page Fault Linear Address |
### CR3
|Bit|Label|Description|[PAE](https://wiki.osdev.org/PAE "PAE")|[Long Mode](https://wiki.osdev.org/Long_Mode "Long Mode")|
|---|---|---|---|---|
|3|PWT|Page-level Write-Through|(Not used)|(Not used if bit 17 of CR4 is 1)|
|4|PCD|Page-level Cache Disable|(Not used)|(Not used if bit 17 of CR4 is 1)|
|12-31 (63)|PDBR|Page Directory Base Register|Base of PDPT|Base of PML4T/PML5T|
### CR4
|Bit|Label|Description|
|---|---|---|
|0|VME|Virtual 8086 Mode Extensions|
|1|PVI|Protected-mode Virtual Interrupts|
|2|TSD|Time Stamp Disable|
|3|DE|Debugging Extensions|
|4|PSE|Page Size Extension|
|5|PAE|Physical Address Extension|
|6|MCE|Machine Check Exception|
|7|PGE|Page Global Enabled|
|8|PCE|Performance-Monitoring Counter enable|
|9|OSFXSR|Operating system support for FXSAVE and FXRSTOR instructions|
|10|OSXMMEXCPT|Operating System Support for Unmasked SIMD Floating-Point Exceptions|
|11|UMIP|User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)|
|12|LA57|57-bit linear addresses (if set, the processor uses 5-level paging otherwise it uses uses 4-level paging)|
|13|VMXE|Virtual Machine Extensions Enable|
|14|SMXE|Safer Mode Extensions Enable|
|16|FSGSBASE|Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE|
|17|PCIDE|PCID Enable|
|18|OSXSAVE|XSAVE and Processor Extended States Enable|
|20|SMEP|[Supervisor Mode Execution Protection](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable|
|21|SMAP|[Supervisor Mode Access Prevention](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable|
|22|PKE|Protection Key Enable|
|23|CET|Control-flow Enforcement Technology|
|24|PKS|Enable Protection Keys for Supervisor-Mode Pages|
### CR8
|Bit|Label|Description|
|---|---|---|
|0-3|TPL|Task Priority Level

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Rings & Privilege Levels.md
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@ -3,5 +3,6 @@ Processors have privilege levels that allow them to enforce access to resources.
The operating system kernel runs at Ring 0 in x86, meaning it has the most privilege of any software on the system. It can bypass the MMU and write to memory directly, it can execute privileged instructions, and it can modify virtual memory mappings. Everything else runs in rings 1 through 3, though 1 and 2 are seldom used. Processes running in Ring 3 can only access memory via the MMU and virtual memory mappings assigned to that process. The operating system kernel runs at Ring 0 in x86, meaning it has the most privilege of any software on the system. It can bypass the MMU and write to memory directly, it can execute privileged instructions, and it can modify virtual memory mappings. Everything else runs in rings 1 through 3, though 1 and 2 are seldom used. Processes running in Ring 3 can only access memory via the MMU and virtual memory mappings assigned to that process.
## Context Switching ## Context Switching
Processes all have unique elements, such as address spaces, stacks, registers, and other things that must be stored and restored. This process is performed by the kernel at a software or hardware defined interval. Processes all have unique elements, such as address spaces, stacks, registers, and other things that must be stored and restored. This process is performed by the kernel at a software or hardware defined interval.
One thing that makes processes distinct is the memory regions, or "[[Physical & Virtual Memory#Pages|Pages]]", that are mapped into their address space. These pages are defined in the page tables- cascading sets of tables, where the address of the root table is stored in the CR3 register. Each process might have its own page table root, which is referenced in CR3 upon a context switch.
### Interrupts & System Calls ### Interrupts & System Calls
Both interrupts and system calls trigger the CPU to pause execution of the current process or task, and resume execution of the kernel. Interrupts are triggered by hardware, such as peripherals or timers, while system calls are triggered by processes. When the CPU attempts to execute a system call instruction while in unprivileged mode, it causes a return to kernel mode. Both interrupts and system calls trigger the CPU to pause execution of the current process or task, and resume execution of the kernel. Interrupts are triggered by hardware, such as peripherals or timers, while system calls are triggered by processes. When the CPU attempts to execute a system call instruction while in unprivileged mode, it causes a return to kernel mode.