From 08002ba0909d396f6ee969ba792d6bd3961437f9 Mon Sep 17 00:00:00 2001
From: shibedrill <shibedrill1@gmail.com>
Date: Fri, 18 Jul 2025 23:15:09 -0400
Subject: [PATCH] License: add license

---
 .gitignore        |   1 +
 Cargo.lock        |  16 ++++++
 Cargo.toml        |   7 +++
 LICENSE           |  18 ++++++
 src/header/mod.rs | 144 ++++++++++++++++++++++++++++++++++++++++++++++
 src/lib.rs        |   1 +
 6 files changed, 187 insertions(+)
 create mode 100644 .gitignore
 create mode 100644 Cargo.lock
 create mode 100644 Cargo.toml
 create mode 100644 LICENSE
 create mode 100644 src/header/mod.rs
 create mode 100644 src/lib.rs

diff --git a/.gitignore b/.gitignore
new file mode 100644
index 0000000..ea8c4bf
--- /dev/null
+++ b/.gitignore
@@ -0,0 +1 @@
+/target
diff --git a/Cargo.lock b/Cargo.lock
new file mode 100644
index 0000000..edf0104
--- /dev/null
+++ b/Cargo.lock
@@ -0,0 +1,16 @@
+# This file is automatically @generated by Cargo.
+# It is not intended for manual editing.
+version = 4
+
+[[package]]
+name = "intbits"
+version = "0.2.0"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "5170c2c8ecda29c1bccb9d95ccbe107bc75fa084dc0c9c6087e719f9d46330e5"
+
+[[package]]
+name = "pci"
+version = "0.1.0"
+dependencies = [
+ "intbits",
+]
diff --git a/Cargo.toml b/Cargo.toml
new file mode 100644
index 0000000..d20afe5
--- /dev/null
+++ b/Cargo.toml
@@ -0,0 +1,7 @@
+[package]
+name = "pci"
+version = "0.1.0"
+edition = "2024"
+
+[dependencies]
+intbits = "0.2.0"
diff --git a/LICENSE b/LICENSE
new file mode 100644
index 0000000..f800ff8
--- /dev/null
+++ b/LICENSE
@@ -0,0 +1,18 @@
+
+# GNU Public License v3
+
+pci - A Rust crate for PCI related data structures.
+Copyright (C) 2025 shibedrill
+
+This program is free software: you can redistribute it and/or modify
+it under the terms of the GNU General Public License as published by
+the Free Software Foundation, either version 3 of the License, or
+(at your option) any later version.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program.  If not, see <https://www.gnu.org/licenses/>.
diff --git a/src/header/mod.rs b/src/header/mod.rs
new file mode 100644
index 0000000..f4fe0c9
--- /dev/null
+++ b/src/header/mod.rs
@@ -0,0 +1,144 @@
+
+use intbits::Bits;
+
+#[repr(u8)]
+pub enum PciHeaderType {
+    GeneralDevice = 0x0,
+    Pci2PciBridge = 0x1,
+    Pci2CardbusBridge = 0x2,
+}
+
+pub enum PciHeader {
+    GeneralDevice(GeneralDeviceHeader),
+    Pci2PciBridge,
+    Pci2CardbusBridge,
+}
+
+pub struct PciHeaderCommon {
+    device_id: u16,
+    vendor_id: u16,
+    status: u16,
+    command: u16,
+    class: u8,
+    subclass: u8,
+    prog_if: u8,
+    revision: u8,
+    bist: u8,
+    header_type: PciHeaderType,
+    latency_timer: u8,
+    cache_line_size: u8,
+}
+
+pub struct GeneralDeviceHeader {
+    common: PciHeaderCommon,
+    bars: [Bar;6],
+    cardbus_cis: u32,
+    subsystem_id: u16,
+    subsystem_vendor_id: u16,
+    erom_addr: u32,
+    _reserved_0: [u8;3],
+    caps: u8,
+    _reserved_1: [u8;4],
+    max_latency: u8,
+    min_grant: u8,
+    interrupt_pin: u8,
+    interrupt_line: u8,
+}
+
+pub struct Pci2PciBridge {
+    common: PciHeaderCommon,
+    bars: [u32;2],
+    secondary_latency_timer: u8,
+    subordinate_bus: u8,
+    secondary_bus: u8,
+    primary_bus: u8,
+    secondary_status: u16,
+    io_limit: u8,
+    io_base: u8,
+    memory_limit: u16,
+    memory_base: u16,
+    prefetch_limit: u16,
+    prefetch_base: u16,
+    prefetch_base_upper: u32,
+    prefetch_limit_upper: u32,
+    io_limit_upper: u16,
+    io_base_upper: u16,
+    _reserved_0: [u8;3],
+    caps: u8,
+    erom_addr: u32,
+    bridge_control: u16,
+    interrupt_pin: u8,
+    interrupt_line: u8,
+}
+
+pub struct Pci2CardbusBridge {
+    common: PciHeaderCommon,
+    cardbus_socket_addr: u32,
+    secondary_status: u16,
+    _reserved_0: u8,
+    caps_offset: u8,
+    cardbus_latency_timer: u8,
+    subordinate_bus: u8,
+    cardbus_bus: u8,
+    pci_bus: u8,
+    mem_base_0: u32,
+    mem_limit_0: u32,
+    mem_base_1: u32,
+    mem_limit_1: u32,
+    io_base_0: u32,
+    io_limit_0: u32,
+    io_base_1: u32,
+    io_limit_1: u32,
+    bridge_control: u16,
+    interrupt_pin: u8,
+    interrupt_line: u8,
+    subsystem_vendor_id: u16,
+    subsystem_device_id: u16,
+    pc_card_base: u32,
+}
+
+pub enum BarType {
+    MemorySpace,
+    IoSpace,
+}
+
+pub enum Bar {
+    MemorySpace(MemorySpaceBar),
+    IoSpace(IoSpaceBar),
+}
+
+impl From<u32> for Bar {
+    fn from(value: u32) -> Self {
+        match value.bit(0) {
+            true => Bar::IoSpace(IoSpaceBar(value)),
+            false => Bar::MemorySpace(MemorySpaceBar(value))
+        }
+    }
+}
+
+pub trait BaseAddress {
+    fn base_address(&self) -> u32;
+}
+pub struct MemorySpaceBar(u32);
+
+impl MemorySpaceBar {
+    pub fn prefetchable(&self) -> bool {
+        self.0.bit(3)
+    }
+    pub fn bar_type(&self) -> u32 {
+        self.0.bits(1..=2)
+    }
+}
+impl BaseAddress for MemorySpaceBar {
+    fn base_address(&self) -> u32 {
+        self.0.bits(4..=31)
+    }
+}
+
+pub struct IoSpaceBar(u32);
+
+impl BaseAddress for IoSpaceBar {
+    fn base_address(&self) -> u32 {
+        self.0.bits(2..=31)
+    }
+}
\ No newline at end of file
diff --git a/src/lib.rs b/src/lib.rs
new file mode 100644
index 0000000..dc93a1c
--- /dev/null
+++ b/src/lib.rs
@@ -0,0 +1 @@
+mod header;
\ No newline at end of file