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Some work on memory

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August 2025-09-25 23:49:32 -04:00
parent 2dad5e11e9
commit fbf6c1a6b9
Signed by: shibedrill
GPG Key ID: 5FE0CB25945EFAA2
3 changed files with 72 additions and 40 deletions
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27
.obsidian/workspace.json vendored
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@ -4,17 +4,21 @@
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@ -90,6 +94,7 @@
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@ -99,7 +104,7 @@
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@ -108,11 +113,12 @@
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@ -136,12 +142,13 @@
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@ -173,7 +180,7 @@
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33
Physical & Virtual Memory.md
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@ -7,6 +7,9 @@ Physical memory on x86 is divided into "Page Frames":
- Can be either 4KiB, 2MiB, or 1GiB depending on the "level" of paging. - Can be either 4KiB, 2MiB, or 1GiB depending on the "level" of paging.
This is a useful abstraction, because pages must be aligned at a multiple of their size - for example, a 2MiB page must be aligned on a 2MiB boundary. In the simplest setup involving 2MiB pages, all of physical memory would be divided into 2MiB page frames for accounting. This is a useful abstraction, because pages must be aligned at a multiple of their size - for example, a 2MiB page must be aligned on a 2MiB boundary. In the simplest setup involving 2MiB pages, all of physical memory would be divided into 2MiB page frames for accounting.
## Virtual Memory & Pages ## Virtual Memory & Pages
In the paging scheme, virtual memory is divided into cascading tables. The depth of the tables will differ depending on which paging mode is enabled. There exists several modes: two-level, three-level, four-level, and five-level paging. The last two require Physical Address Extensions.
### Pages
A page is a virtual, contiguous segment of memory, which is backed by exactly one page frame. A page is defined by its entry in a page table, or page directory, each of which may contain up to 4096 pages.
### 32-Bit Paging ### 32-Bit Paging
32-Bit Paging involves two tables, or two "levels", that are traversed to determine the physical location of a logical address. The first table is the "Page Directory", and each entry in the page directory points to a "Page Table", which contains entries pointing to physical frames. In a sense, each entry in the page table is a page, in that it represents one physical page frame. 32-Bit Paging involves two tables, or two "levels", that are traversed to determine the physical location of a logical address. The first table is the "Page Directory", and each entry in the page directory points to a "Page Table", which contains entries pointing to physical frames. In a sense, each entry in the page table is a page, in that it represents one physical page frame.
Both the page directory, and each page table, contains 1024 4-byte (32-bit) entries. Overall, the page directory is 4096KiB, and so is each page table. Both the page directory, and each page table, contains 1024 4-byte (32-bit) entries. Overall, the page directory is 4096KiB, and so is each page table.
@ -16,12 +19,12 @@ Each page directory entry looks like this:
| 31..=12 | 11..=8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | 31..=12 | 11..=8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ----------------------- | ------ | ---- | --- | --- | --- | --- | --- | --- | --- | | ----------------------- | ------ | ---- | --- | --- | --- | --- | --- | --- | --- |
| Bits 31..=12 of address | AVL | PS=1 | AVL | A | PCD | PWT | U/S | R/W | P | | Bits 31..=12 of address | AVL | PS=0 | AVL | A | PCD | PWT | U/S | R/W | P |
If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table. If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table.
| 31..=22 | 21 | 20..=13 | 12 | 11..=9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 | | 31..=22 | 21 | 20..=13 | 12 | 11..=9 | 8 | 7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
| ----------------------- | ---- | ----------------------- | --- | ------ | --- | ---- | --- | --- | --- | --- | --- | --- | --- | | ----------------------- | ---- | ----------------------- | --- | ------ | --- | ---- | --- | --- | --- | --- | --- | --- | --- |
| Bits 31..=22 of address | RSVD | Bits 39..=32 of address | PAT | AVL | G | PS=0 | D | A | PCD | PWT | U/S | R/W | P | | Bits 31..=22 of address | RSVD | Bits 39..=32 of address | PAT | AVL | G | PS=1 | D | A | PCD | PWT | U/S | R/W | P |
If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table. If the Page Size bit is set, the entry refers directly to a 4MiB page, instead of a page table.
Here are the keys and their meanings: Here are the keys and their meanings:
- RSVD: Reserved - Must be set to 0, otherwise, will cause a page fault. - RSVD: Reserved - Must be set to 0, otherwise, will cause a page fault.
@ -35,8 +38,30 @@ Here are the keys and their meanings:
- PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table. - PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table.
- G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified. - G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified.
- AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits. - AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits.
#### Pages #### 32-Bit PAE
A page is a virtual, contiguous segment of memory, which is backed by exactly one page frame. A page is defined by its entry in a page table, or page directory, each of which may contain up to 4096 pages. If Physical Address Extensions is enabled, then 3-level paging is used. In 3-level paging, instead of the root table being a page directory, it will be a Page Directory Pointer Table, which is a list of 4 64-bit entries. Each entry refers to a page directory, full of 512 64-bit entries. Each page directory entry points to a page table, which is full of 512 64-bit page entries.
## 64-Bit Paging
Requires Physical Address Extensions (PAE). 64-bit paging enables the use of 3, 4, and 5-level paging.
```
CR3
└─ PML5 Table: 512 * 64-bit entries
└─ PML4 Table: 512 * 64-bit entries
└─ PDP Table: 4 * 64-bit entries
└─ Page Directory: 512 * 64-bit entries
└─ Page Table: 512 * 64-bit entries
└─ Page
```
```rust
type Page: u64; // Page reference is 64 bits, stores address and flags of an individual page
type PageTable: [u64;512]; // Page Table entry is 64 bits, refers to a Page
type PageDirectory: [u64;512]; // Page Directory entry is 64 bits, refers to a PageTable
type PDPTable: [u64;512]; // Page Directory Pointer Table entry is 64 bits, refers to a Page Directory
type PML4Table: [u64;512]; // Page Map Level 4 Table entry is 64 bits, refers to a Page Directory Pointer Table
type PML5Table: [u64;512];
// CR3 holds a reference to the root PML5Table
```
#### Address Translation Example #### Address Translation Example
If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address), the MMU would separate the address into three parts. If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address), the MMU would separate the address into three parts.
Address: `0xdeadbeef` / `0b11011110101011011011111011101111` Address: `0xdeadbeef` / `0b11011110101011011011111011101111`

52
Registers.md
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@ -20,7 +20,7 @@ Used infrequently by the kernel when performing context switches.
| ------ | ------ | ------ | ------------------- | | ------ | ------ | ------ | ------------------- |
| RIP | EIP | IP | Instruction Pointer | | RIP | EIP | IP | Instruction Pointer |
## Segment Registers ## Segment Registers
Used more often when doing memory segmentation, as opposed to paging. Still required when doing paging, since you still need a GDT. Used more often when doing memory segmentation, as opposed to paging.
| 16-bit | Description | | 16-bit | Description |
| ------ | ------------------------- | | ------ | ------------------------- |
@ -79,31 +79,31 @@ These special registers are set by the CPU and, on occasion, modified to change
|4|PCD|Page-level Cache Disable|(Not used)|(Not used if bit 17 of CR4 is 1)| |4|PCD|Page-level Cache Disable|(Not used)|(Not used if bit 17 of CR4 is 1)|
|12-31 (63)|PDBR|Page Directory Base Register|Base of PDPT|Base of PML4T/PML5T| |12-31 (63)|PDBR|Page Directory Base Register|Base of PDPT|Base of PML4T/PML5T|
### CR4 ### CR4
|Bit|Label|Description| | Bit | Label | Description |
|---|---|---| | --- | ---------- | --------------------------------------------------------------------------------------------------------------------------------- |
|0|VME|Virtual 8086 Mode Extensions| | 0 | VME | Virtual 8086 Mode Extensions |
|1|PVI|Protected-mode Virtual Interrupts| | 1 | PVI | Protected-mode Virtual Interrupts |
|2|TSD|Time Stamp Disable| | 2 | TSD | Time Stamp Disable |
|3|DE|Debugging Extensions| | 3 | DE | Debugging Extensions |
|4|PSE|Page Size Extension| | 4 | PSE | Page Size Extension |
|5|PAE|Physical Address Extension| | 5 | PAE | Physical Address Extension |
|6|MCE|Machine Check Exception| | 6 | MCE | Machine Check Exception |
|7|PGE|Page Global Enabled| | 7 | PGE | Page Global Enabled |
|8|PCE|Performance-Monitoring Counter enable| | 8 | PCE | Performance-Monitoring Counter enable |
|9|OSFXSR|Operating system support for FXSAVE and FXRSTOR instructions| | 9 | OSFXSR | Operating system support for FXSAVE and FXRSTOR instructions |
|10|OSXMMEXCPT|Operating System Support for Unmasked SIMD Floating-Point Exceptions| | 10 | OSXMMEXCPT | Operating System Support for Unmasked SIMD Floating-Point Exceptions |
|11|UMIP|User-Mode Instruction Prevention (if set, #GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0)| | 11 | UMIP | User-Mode Instruction Prevention (if set, \#GP on SGDT, SIDT, SLDT, SMSW, and STR instructions when CPL > 0) |
|12|LA57|57-bit linear addresses (if set, the processor uses 5-level paging otherwise it uses uses 4-level paging)| | 12 | LA57 | 57-bit linear addresses (if set, the processor uses 5-level paging otherwise it uses uses 4-level paging) |
|13|VMXE|Virtual Machine Extensions Enable| | 13 | VMXE | Virtual Machine Extensions Enable |
|14|SMXE|Safer Mode Extensions Enable| | 14 | SMXE | Safer Mode Extensions Enable |
|16|FSGSBASE|Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE| | 16 | FSGSBASE | Enables the instructions RDFSBASE, RDGSBASE, WRFSBASE, and WRGSBASE |
|17|PCIDE|PCID Enable| | 17 | PCIDE | PCID Enable |
|18|OSXSAVE|XSAVE and Processor Extended States Enable| | 18 | OSXSAVE | XSAVE and Processor Extended States Enable |
|20|SMEP|[Supervisor Mode Execution Protection](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable| | 20 | SMEP | [Supervisor Mode Execution Protection](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable |
|21|SMAP|[Supervisor Mode Access Prevention](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable| | 21 | SMAP | [Supervisor Mode Access Prevention](https://wiki.osdev.org/Supervisor_Memory_Protection "Supervisor Memory Protection") Enable |
|22|PKE|Protection Key Enable| | 22 | PKE | Protection Key Enable |
|23|CET|Control-flow Enforcement Technology| | 23 | CET | Control-flow Enforcement Technology |
|24|PKS|Enable Protection Keys for Supervisor-Mode Pages| | 24 | PKS | Enable Protection Keys for Supervisor-Mode Pages |
### CR8 ### CR8
|Bit|Label|Description| |Bit|Label|Description|
|---|---|---| |---|---|---|