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Physical & Virtual Memory.md
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@ -7,7 +7,7 @@ Physical memory on x86 is divided into "Page Frames":
- Can be either 4KiB, 2MiB, or 1GiB depending on the "level" of paging. - Can be either 4KiB, 2MiB, or 1GiB depending on the "level" of paging.
This is a useful abstraction, because pages must be aligned at a multiple of their size - for example, a 2MiB page must be aligned on a 2MiB boundary. In the simplest setup involving 2MiB pages, all of physical memory would be divided into 2MiB page frames for accounting. This is a useful abstraction, because pages must be aligned at a multiple of their size - for example, a 2MiB page must be aligned on a 2MiB boundary. In the simplest setup involving 2MiB pages, all of physical memory would be divided into 2MiB page frames for accounting.
## Virtual Memory & Pages ## Virtual Memory & Pages
In the paging scheme, virtual memory is divided into cascading tables. The depth of the tables will differ depending on which paging mode is enabled. There exists several modes: two-level, three-level, four-level, and five-level paging. The last two require Physical Address Extensions. In the paging scheme, virtual memory is divided into cascading tables. The depth of the tables will differ depending on which paging mode is enabled. There exists several modes: two-level, three-level, four-level, and five-level paging. The last two require Physical Address Extensions, as well as 64-bit virtual addresses.
### Pages ### Pages
A page is a virtual, contiguous segment of memory, which is backed by exactly one page frame. A page is defined by its entry in a page table, or page directory, each of which may contain up to 4096 pages. A page is a virtual, contiguous segment of memory, which is backed by exactly one page frame. A page is defined by its entry in a page table, or page directory, each of which may contain up to 4096 pages.
### 32-Bit Paging ### 32-Bit Paging
@ -38,6 +38,13 @@ Here are the keys and their meanings:
- PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table. - PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table.
- G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified. - G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified.
- AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits. - AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits.
#### Address Translation Example
If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address, using 2-level paging without PAE), the MMU would separate the address into three parts.
Address: `0xdeadbeef` / `0b11011110101011011011111011101111`
First 10 bits: `0b1101111010` / 890 - Page Directory Offset (Page Table)
Next 10 bits: `0b1011011011` / 731 - Page Table Offset (Page Table Entry)
Last 12 bits: `0b111011101111` / 3823 - Offset from start of page
So the MMU would search for the 3,823rd byte, of the 731st page, of the 890th page table.
#### 32-Bit PAE #### 32-Bit PAE
If Physical Address Extensions is enabled, then 3-level paging is used. In 3-level paging, instead of the root table being a page directory, it will be a Page Directory Pointer Table, which is a list of 4 64-bit entries. Each entry refers to a page directory, full of 512 64-bit entries. Each page directory entry points to a page table, which is full of 512 64-bit page entries. If Physical Address Extensions is enabled, then 3-level paging is used. In 3-level paging, instead of the root table being a page directory, it will be a Page Directory Pointer Table, which is a list of 4 64-bit entries. Each entry refers to a page directory, full of 512 64-bit entries. Each page directory entry points to a page table, which is full of 512 64-bit page entries.
## 64-Bit Paging ## 64-Bit Paging
@ -62,10 +69,3 @@ type PML4Table: [u64;512]; // Page Map Level 4 Table entry is 64 bits, refers to
type PML5Table: [u64;512]; type PML5Table: [u64;512];
// CR3 holds a reference to the root PML5Table // CR3 holds a reference to the root PML5Table
``` ```
#### Address Translation Example
If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address), the MMU would separate the address into three parts.
Address: `0xdeadbeef` / `0b11011110101011011011111011101111`
First 10 bits: `0b1101111010` / 890 - Page Directory Offset (Page Table)
Next 10 bits: `0b1011011011` / 731 - Page Table Offset (Page Table Entry)
Last 12 bits: `0b111011101111` / 3823 - Offset from start of page
So the MMU would search for the 3,823rd byte, of the 731st page, of the 890th page table.