ToC

.obsidian/workspace.json

@@ -10,6 +10,20 @@
           {
             "id": "fcb894c66b7bc94f",
             "type": "leaf",
+            "state": {
+              "type": "markdown",
+              "state": {
+                "file": "Welcome.md",
+                "mode": "source",
+                "source": false
+              },
+              "icon": "lucide-file",
+              "title": "Welcome"
+            }
+          },
+          {
+            "id": "03a1d09568f1c625",
+            "type": "leaf",
             "state": {
               "type": "markdown",
               "state": {
@@ -94,7 +108,7 @@
             "state": {
               "type": "backlink",
               "state": {
-                "file": "Physical & Virtual Memory.md",
+                "file": "Welcome.md",
                 "collapseAll": false,
                 "extraContext": false,
                 "sortOrder": "alphabetical",
@@ -104,7 +118,7 @@
                 "unlinkedCollapsed": true
               },
               "icon": "links-coming-in",
-              "title": "Backlinks for Physical & Virtual Memory"
+              "title": "Backlinks for Welcome"
             }
           },
           {
@@ -113,12 +127,12 @@
             "state": {
               "type": "outgoing-link",
               "state": {
-                "file": "Physical & Virtual Memory.md",
+                "file": "Welcome.md",
                 "linksCollapsed": false,
                 "unlinkedCollapsed": true
               },
               "icon": "links-going-out",
-              "title": "Outgoing links from Physical & Virtual Memory"
+              "title": "Outgoing links from Welcome"
             }
           },
           {
@@ -142,13 +156,13 @@
             "state": {
               "type": "outline",
               "state": {
-                "file": "Physical & Virtual Memory.md",
+                "file": "Welcome.md",
                 "followCursor": false,
                 "showSearch": false,
                 "searchQuery": ""
               },
               "icon": "lucide-list",
-              "title": "Outline of Physical & Virtual Memory"
+              "title": "Outline of Welcome"
             }
           },
           {
@@ -182,10 +196,10 @@
   },
   "active": "fcb894c66b7bc94f",
   "lastOpenFiles": [
-    "Registers.md",
     "Physical & Virtual Memory.md",
+    "Welcome.md",
+    "Registers.md",
     "Rings & Privilege Levels.md",
-    "create a link.md",
+    "create a link.md"
-    "Welcome.md"
   ]
 }

Physical & Virtual Memory.md

@@ -15,7 +15,7 @@ A page is a virtual, contiguous segment of memory, which is backed by exactly on
 Both the page directory, and each page table, contains 1024 4-byte (32-bit) entries. Overall, the page directory is 4096KiB, and so is each page table.
 In 32-bit paging mode, bits 12..=31 of the register CR3 indicate the address of the root page directory.
 
-Each page directory entry looks like this:
+Each page directory entry looks like this. It points to a Page Table.
 
 | 31..=12                 | 11..=8 | 7    | 6   | 5   | 4   | 3   | 2   | 1   | 0   |
 | ----------------------- | ------ | ---- | --- | --- | --- | --- | --- | --- | --- |
@@ -38,6 +38,7 @@ Here are the keys and their meanings:
 - PS: Page Size - Set to 1 if the entry refers to a 4MiB page, instead of 1,024 4KiB pages stored in the referenced page table.
 - G: Global - If set to 1, the processor will not invalidate the relevant TLB entry if CR3 is modified.
 - AVL: Available - Unused by the CPU, and can be used by the OS. As far as I know, nothing popular uses these bits.
+- PAT: Page Attribute Table - If set to 1, enables different behavior for caching than is possible to configure using solely PCD and PWT. When enabled, the bits PAT, PCD, and PWT are combined into a 3-bit index into a list of cache behaviors.
 #### Address Translation Example
 If a process wanted to access the virtual address `0xdeadbeef` (a 32-bit virtual address, using 2-level paging without PAE), the MMU would separate the address into three parts.
 Address: `0xdeadbeef` / `0b11011110101011011011111011101111`
@@ -47,7 +48,7 @@ Last 12 bits: `0b111011101111` / 3823 - Offset from start of page
 So the MMU would search for the 3,823rd byte, of the 731st page, of the 890th page table.
 #### 32-Bit PAE
 If Physical Address Extensions is enabled, then 3-level paging is used. In 3-level paging, instead of the root table being a page directory, it will be a Page Directory Pointer Table, which is a list of 4 64-bit entries. Each entry refers to a page directory, full of 512 64-bit entries. Each page directory entry points to a page table, which is full of 512 64-bit page entries. 
-## 64-Bit Paging
+### 64-Bit Paging
 Requires Physical Address Extensions (PAE). 64-bit paging enables the use of 3, 4, and 5-level paging.
 
 ```
@@ -68,4 +69,23 @@ type PDPTable: [u64;512]; // Page Directory Pointer Table entry is 64 bits, refe
 type PML4Table: [u64;512]; // Page Map Level 4 Table entry is 64 bits, refers to a Page Directory Pointer Table
 type PML5Table: [u64;512];
 // CR3 holds a reference to the root PML5Table
-```
+```
+
+Page Directory Pointer Table Entries look like this. They point to a Page Directory.
+
+| 63  | 62..=59 | 58..=52 | 51..=M | (M-1)..=30                 | 29..=13 | 12  | 11..=9 | 8   | 7    | 6   | 5   | 4   | 3   | 2   | 1   | 0   |
+| --- | ------- | ------- | ------ | -------------------------- | ------- | --- | ------ | --- | ---- | --- | --- | --- | --- | --- | --- | --- |
+| XD  | PK      | AVL     | RSVD   | Bits 30..=(M-1) of address | RSVD    | PAT | AVL    | G   | PS=1 | D   | A   | PCD | PWT | U/S | R/W | P   |
+Page Directory Entries look like this. They point to Page Tables.
+
+| 63  | 62..=59 | 58..=52 | 51..=M | (M-1)..=21                 | 20..=13 | 12  | 11..=9 | 8   | 7    | 6   | 5   | 4   | 3   | 2   | 1   | 0   |
+| --- | ------- | ------- | ------ | -------------------------- | ------- | --- | ------ | --- | ---- | --- | --- | --- | --- | --- | --- | --- |
+| XD  | PK      | AVL     | RSVD   | Bits 21..=(M-1) of address | RSVD    | PAT | AVL    | G   | PS=1 | D   | A   | PCD | PWT | U/S | R/W | P   |
+Page Table Entries look like this. They point to individual pages.
+
+| 63  | 62..=59 | 58..=52 | 51..=M | (M-1)..=12                 | 11..=9 | 8   | 7   | 6   | 5   | 4   | 3   | 2   | 1   | 0   |
+| --- | ------- | ------- | ------ | -------------------------- | ------ | --- | --- | --- | --- | --- | --- | --- | --- | --- |
+| XD  | PK      | AVL     | RSVD   | Bits 12..=(M-1) of address | AVL    | G   | PAT | D   | A   | PCD | PWT | U/S | R/W | P   |
+Some additional keys:
+- XD: Execute Disable - If the CPU supports the Execute Disable bit, then the CPU will fault when trying to execute at an address within a page, if the XD bit is set for that page.
+- PK: Protection Key - 

Welcome.md

@@ -1,5 +1,26 @@
-This is your new *vault*.
+These are my personal notes on OS development, part of my [Gila microkernel project](https://git.shibedrill.site/shibedrill/gila).
 
-Make a note of something, [[create a link]], or try [the Importer](https://help.obsidian.md/Plugins/Importer)!
+## Table of Contents
-
+- [[Physical & Virtual Memory]]
-When you're ready, delete this note and make the vault your own.
+	- [[Physical & Virtual Memory#Physical Memory|Physical Memory]]
+	- [[Physical & Virtual Memory#Virtual Memory & Pages|Virtual Memory & Pages]]
+		- [[Physical & Virtual Memory#Pages|Pages]]
+		- [[Physical & Virtual Memory#32-Bit Paging|32-Bit Paging]]
+			- [[Physical & Virtual Memory#Address Translation Example|Address Translation Example]]
+			- [[Physical & Virtual Memory#32-Bit PAE|32-Bit PAE]]
+		- [[Physical & Virtual Memory#64-Bit Paging|64-Bit Paging]]
+- [[Registers]]
+	- [[Registers#General Purpose Registers|General Purpose Registers]]
+	- [[Registers#Pointer Registers|Pointer Registers]]
+	- [[Registers#Segment Registers|Segment Registers]]
+	- [[Registers#EFLAGS Register|EFLAGS Register]]
+	- [[Registers#Control Registers|Control Registers]]
+		- [[Registers#CR0|CR0]]
+		- [[Registers#CR2|CR2]]
+		- [[Registers#CR3|CR3]]
+		- [[Registers#CR4|CR4]]
+		- [[Registers#CR8|CR8]]
+- [[Rings & Privilege Levels]]
+	- [[Rings & Privilege Levels#Process vs. Kernel|Process vs. Kernel]]
+	- [[Rings & Privilege Levels#Context Switching|Context Switching]]
+	- [[Rings & Privilege Levels#Interrupts & System Calls|Interrupts & System Calls]]