Remove extraneous page table code
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c8886495a2
commit
90daf095f0
GPG Key ID:
5FE0CB25945EFAA2
@ -14,7 +14,7 @@ compile_error!(
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#[cfg(target_arch = "x86_64")]
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pub mod x86_64;
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#[cfg(target_arch = "x86_64")]
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pub use x86_64::{asm, paging};
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pub use x86_64::asm;
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#[cfg(target_arch = "aarch64")]
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pub mod aarch64;
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@ -1,256 +1,37 @@
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#![allow(dead_code)]
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use crate::{log_info, log_trace, LogLevel, LOGGER, format};
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use crate::memory::HHDM_RESPONSE;
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use crate::arch;
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use intbits::Bits;
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use x86_64::structures::paging::page_table;
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use x86_64::structures::paging::page_table::PageTable;
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use x86_64::structures::paging::PageTableFlags;
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pub struct PageMapLevel5 {
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entries: [PageMapLevel5Entry; 512],
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}
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pub fn get_mappings() {
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log_info!("HHDM offset: 0x{:X}", HHDM_RESPONSE.offset());
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pub struct PageMapLevel5Entry {
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value: u64,
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log_info!("Paging: {}", arch::asm::read_cr0().bit(31));
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log_info!("Protection: {}", arch::asm::read_cr0().bit(0));
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log_info!(
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"Physical Address Extensions: {}",
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arch::asm::read_cr4().bit(5)
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);
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log_info!("Page Size Extensions: {}", arch::asm::read_cr4().bit(4));
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log_info!(
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"Paging mode: {}",
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match crate::memory::PAGING_REQUEST.get_response().unwrap().mode() {
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limine::paging::Mode::FOUR_LEVEL => "Four-Level",
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limine::paging::Mode::FIVE_LEVEL => "Five-Level",
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_ => unreachable!(),
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}
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);
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log_info!("CR3 Value: 0b{:064b}", arch::asm::read_cr3());
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// Physical address of Page Map Level 4 Table
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let pml4_ptr: *const PageTable = ((arch::asm::read_cr3().bits(12..=63) << 12) + HHDM_RESPONSE.offset()) as *const PageTable;
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let pagemap_lvl4 = unsafe { &*pml4_ptr };
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for entry in pagemap_lvl4.iter() {
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if entry.flags().contains(PageTableFlags::PRESENT) {
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log_trace!("Page Table Level 4 Entry: 0x{:X}", entry.addr());
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}
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impl PageMapLevel5Entry {
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pub fn execute_disable(&self) -> bool {
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self.value.bit(63)
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}
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pub fn present(&self) -> bool {
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self.value.bit(0)
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}
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pub fn set_present(&mut self, present: bool) {
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self.value.set_bit(0, present);
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}
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pub fn writable(&self) -> bool {
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self.value.bit(1)
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}
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pub fn set_writable(&mut self, writable: bool) {
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self.value.set_bit(1, writable);
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}
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pub fn user_accessible(&self) -> bool {
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self.value.bit(2)
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}
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pub fn set_user_accessible(&mut self, accessible: bool) {
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self.value.set_bit(2, accessible);
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}
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pub fn write_through(&self) -> bool {
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self.value.bit(3)
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}
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pub fn set_write_through(&mut self, write_through: bool) {
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self.value.set_bit(3, write_through);
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}
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pub fn cache_disable(&self) -> bool {
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self.value.bit(4)
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}
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pub fn set_cache_disable(&mut self, cache_disable: bool) {
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self.value.set_bit(4, cache_disable);
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}
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pub fn accessed(&self) -> bool {
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self.value.bit(5)
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}
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pub fn set_accessed(&mut self, accessed: bool) {
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self.value.set_bit(5, accessed);
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}
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pub fn physical_address(&self) -> usize {
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self.value.bits(12..=51) as usize
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}
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pub fn set_physical_address(&mut self, address: u64) {
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self.value &= 0xFFF0000000000FFF;
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self.value |= (address & 0xFFFFFFFFFF) << 12;
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}
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pub fn available(&self) -> usize {
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(self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
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as usize
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}
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}
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pub struct PageMapLevel4 {
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pub entries: [PageMapLevel4Entry; 512],
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}
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pub struct PageMapLevel4Entry {
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value: u64,
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}
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impl PageMapLevel4Entry {
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pub fn execute_disable(&self) -> bool {
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self.value.bit(63)
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}
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pub fn present(&self) -> bool {
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self.value.bit(0)
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}
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pub fn set_present(&mut self, present: bool) {
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self.value.set_bit(0, present);
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}
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pub fn writable(&self) -> bool {
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self.value.bit(1)
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}
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pub fn set_writable(&mut self, writable: bool) {
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self.value.set_bit(1, writable);
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}
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pub fn user_accessible(&self) -> bool {
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self.value.bit(2)
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}
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pub fn set_user_accessible(&mut self, accessible: bool) {
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self.value.set_bit(2, accessible);
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}
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pub fn write_through(&self) -> bool {
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self.value.bit(3)
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}
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pub fn set_write_through(&mut self, write_through: bool) {
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self.value.set_bit(3, write_through);
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}
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pub fn cache_disable(&self) -> bool {
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self.value.bit(4)
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}
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pub fn set_cache_disable(&mut self, cache_disable: bool) {
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self.value.set_bit(4, cache_disable);
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}
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pub fn accessed(&self) -> bool {
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self.value.bit(5)
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}
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pub fn set_accessed(&mut self, accessed: bool) {
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self.value.set_bit(5, accessed);
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}
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pub fn physical_address(&self) -> usize {
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self.value.bits(12..=51) as usize
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}
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pub fn set_physical_address(&mut self, address: u64) {
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self.value &= 0xFFF0000000000FFF;
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self.value |= (address & 0xFFFFFFFFFF) << 12;
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}
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pub fn set_pointer_table(&mut self, table: &PageDirectoryPointerTable) {
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self.set_physical_address(&raw const table as u64);
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}
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pub fn available(&self) -> usize {
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(self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
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as usize
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}
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}
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pub struct PageDirectoryPointerTable {
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entries: [*mut PageDirectory; 4],
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}
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pub struct PageDirectoryPointer {
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value: u64,
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}
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impl PageDirectoryPointer {
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pub fn execute_disable(&self) -> bool {
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self.value.bit(63)
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}
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pub fn present(&self) -> bool {
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self.value.bit(0)
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}
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pub fn set_present(&mut self, present: bool) {
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self.value.set_bit(0, present);
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}
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pub fn writable(&self) -> bool {
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self.value.bit(1)
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}
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pub fn set_writable(&mut self, writable: bool) {
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self.value.set_bit(1, writable);
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}
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pub fn user_accessible(&self) -> bool {
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self.value.bit(2)
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}
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pub fn set_user_accessible(&mut self, accessible: bool) {
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self.value.set_bit(2, accessible);
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}
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pub fn write_through(&self) -> bool {
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self.value.bit(3)
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}
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pub fn set_write_through(&mut self, write_through: bool) {
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self.value.set_bit(3, write_through);
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}
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pub fn cache_disable(&self) -> bool {
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self.value.bit(4)
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}
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pub fn set_cache_disable(&mut self, cache_disable: bool) {
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self.value.set_bit(4, cache_disable);
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}
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pub fn accessed(&self) -> bool {
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self.value.bit(5)
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}
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pub fn set_accessed(&mut self, accessed: bool) {
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self.value.set_bit(5, accessed);
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}
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pub fn physical_address(&self) -> *mut PageDirectory {
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self.value.bits(12..=51) as *mut PageDirectory
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}
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pub fn set_physical_address(&mut self, address: u64) {
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self.value &= 0xFFF0000000000FFF;
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self.value |= (address & 0xFFFFFFFFFF) << 12;
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}
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pub fn set_page_directory(&mut self, dir: &PageDirectory) {
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self.set_physical_address(&raw const dir as u64);
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}
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pub fn available(&self) -> usize {
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(self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
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as usize
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}
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}
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pub struct PageDirectory {
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entries: [PageDirectoryEntry; 512],
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}
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pub struct PageDirectoryEntry {
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value: u64,
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}
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impl PageDirectoryEntry {
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pub fn execute_disable(&self) -> bool {
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self.value.bit(63)
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}
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pub fn present(&self) -> bool {
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self.value.bit(0)
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}
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pub fn set_present(&mut self, present: bool) {
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self.value.set_bit(0, present);
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}
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pub fn writable(&self) -> bool {
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self.value.bit(1)
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}
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pub fn set_writable(&mut self, writable: bool) {
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self.value.set_bit(1, writable);
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}
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pub fn user_accessible(&self) -> bool {
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self.value.bit(2)
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}
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pub fn set_user_accessible(&mut self, accessible: bool) {
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self.value.set_bit(2, accessible);
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}
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pub fn write_through(&self) -> bool {
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self.value.bit(3)
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}
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pub fn set_write_through(&mut self, write_through: bool) {
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self.value.set_bit(3, write_through);
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}
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pub fn cache_disable(&self) -> bool {
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self.value.bit(4)
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}
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pub fn set_cache_disable(&mut self, cache_disable: bool) {
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self.value.set_bit(4, cache_disable);
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}
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pub fn accessed(&self) -> bool {
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self.value.bit(5)
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}
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pub fn set_accessed(&mut self, accessed: bool) {
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self.value.set_bit(5, accessed);
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}
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pub fn physical_address(&self) -> usize {
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self.value.bits(12..=51) as usize
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}
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pub fn set_physical_address(&mut self, address: u64) {
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self.value &= 0xFFF0000000000FFF;
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self.value |= (address & 0xFFFFFFFFFF) << 12;
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}
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pub fn available(&self) -> usize {
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(self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
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as usize
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}
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}
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pub use page_table::PageTable;
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@ -25,18 +25,16 @@ use arch::x86_64::serial::Serialport;
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use boot::{modules::*, params, *};
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use constants::*;
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use intbits::Bits;
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use limine::firmware_type::FirmwareType;
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use log::*;
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use memory::alloc::{format, string::*, vec};
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use memory::{HHDM_RESPONSE, MEMMAP_REQUEST};
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use memory::MEMMAP_REQUEST;
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use params::*;
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use limine::memory_map::EntryType;
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#[allow(unused_imports)]
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use lzma_rs::lzma_decompress;
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use crate::arch::paging::PageMapLevel4;
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use crate::arch::x86_64::interrupts::IDT;
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#[unsafe(no_mangle)]
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@ -201,31 +199,7 @@ unsafe extern "C" fn main() -> ! {
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panic!("Memory map contains no entries");
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}
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log_info!("HHDM offset: 0x{:X}", HHDM_RESPONSE.offset());
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log_info!("Paging: {}", arch::asm::read_cr0().bit(31));
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log_info!("Protection: {}", arch::asm::read_cr0().bit(0));
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log_info!(
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"Physical Address Extensions: {}",
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arch::asm::read_cr4().bit(5)
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);
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log_info!("Page Size Extensions: {}", arch::asm::read_cr4().bit(4));
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log_info!(
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"Paging mode: {}",
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match memory::PAGING_REQUEST.get_response().unwrap().mode() {
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limine::paging::Mode::FOUR_LEVEL => "Four-Level",
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limine::paging::Mode::FIVE_LEVEL => "Five-Level",
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_ => unreachable!(),
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}
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);
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log_info!("CR3 Value: 0b{:064b}", arch::asm::read_cr3());
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// Physical address of Page Map Level 4 Table
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let pml4_ptr = ((arch::asm::read_cr3().bits(12..=63) << 12) + HHDM_RESPONSE.offset())
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as *const PageMapLevel4;
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log_info!("Page Map Level 4 Table Address: 0x{:x}", pml4_ptr.addr());
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log_info!("Physical address of first entry: {}", unsafe {
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(*pml4_ptr).entries[0].physical_address()
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});
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arch::x86_64::paging::get_mappings();
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panic!("Bailing");
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@ -1,7 +1,6 @@
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// Copyright (c) 2025 shibedrill
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// SPDX-License-Identifier: GPL-3.0-or-later
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use crate::arch::paging::{PageDirectory, PageTable};
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use crate::memory::alloc;
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use alloc::string::String;
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use alloc::vec::Vec;
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@ -28,12 +27,6 @@ pub struct Process {
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stack_length: usize,
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/// The stack pointer, which is relative to the memory region start.
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stack_pointer: usize,
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/// The page direcory pointing to this process's pages.
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page_directory: PageDirectory,
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/// All pages owned by the process.
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/// When creating a process, we should create one read-write data page,
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/// with execution disabled, and one read-only executable page.
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page_tables: Vec<PageTable>,
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/// Process priority. Lower number is higher priority.
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priority: u16,
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}
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