Remove extraneous page table code

src/kernel/arch/mod.rs

@@ -14,7 +14,7 @@ compile_error!(
 #[cfg(target_arch = "x86_64")]
 pub mod x86_64;
 #[cfg(target_arch = "x86_64")]
-pub use x86_64::{asm, paging};
+pub use x86_64::asm;
 
 #[cfg(target_arch = "aarch64")]
 pub mod aarch64;

src/kernel/arch/x86_64/paging.rs

@@ -1,256 +1,37 @@
 #![allow(dead_code)]
 
+use crate::{log_info, log_trace, LogLevel, LOGGER, format};
+use crate::memory::HHDM_RESPONSE;
+use crate::arch;
 use intbits::Bits;
-use x86_64::structures::paging::page_table;
+use x86_64::structures::paging::page_table::PageTable;
+use x86_64::structures::paging::PageTableFlags;
 
-pub struct PageMapLevel5 {
+pub fn get_mappings() {
-    entries: [PageMapLevel5Entry; 512],
+    log_info!("HHDM offset: 0x{:X}", HHDM_RESPONSE.offset());
-}
 
-pub struct PageMapLevel5Entry {
+    log_info!("Paging: {}", arch::asm::read_cr0().bit(31));
-    value: u64,
+    log_info!("Protection: {}", arch::asm::read_cr0().bit(0));
-}
+    log_info!(
-
+        "Physical Address Extensions: {}",
-impl PageMapLevel5Entry {
+        arch::asm::read_cr4().bit(5)
-    pub fn execute_disable(&self) -> bool {
+    );
-        self.value.bit(63)
+    log_info!("Page Size Extensions: {}", arch::asm::read_cr4().bit(4));
+    log_info!(
+        "Paging mode: {}",
+        match crate::memory::PAGING_REQUEST.get_response().unwrap().mode() {
+            limine::paging::Mode::FOUR_LEVEL => "Four-Level",
+            limine::paging::Mode::FIVE_LEVEL => "Five-Level",
+            _ => unreachable!(),
         }
-    pub fn present(&self) -> bool {
+    );
-        self.value.bit(0)
+    log_info!("CR3 Value: 0b{:064b}", arch::asm::read_cr3());
+    // Physical address of Page Map Level 4 Table
+    let pml4_ptr: *const PageTable = ((arch::asm::read_cr3().bits(12..=63) << 12) + HHDM_RESPONSE.offset()) as *const PageTable;
+    let pagemap_lvl4 = unsafe { &*pml4_ptr };
+    for entry in pagemap_lvl4.iter() {
+        if entry.flags().contains(PageTableFlags::PRESENT) {
+            log_trace!("Page Table Level 4 Entry: 0x{:X}", entry.addr());
         }
-    pub fn set_present(&mut self, present: bool) {
-        self.value.set_bit(0, present);
-    }
-    pub fn writable(&self) -> bool {
-        self.value.bit(1)
-    }
-    pub fn set_writable(&mut self, writable: bool) {
-        self.value.set_bit(1, writable);
-    }
-    pub fn user_accessible(&self) -> bool {
-        self.value.bit(2)
-    }
-    pub fn set_user_accessible(&mut self, accessible: bool) {
-        self.value.set_bit(2, accessible);
-    }
-    pub fn write_through(&self) -> bool {
-        self.value.bit(3)
-    }
-    pub fn set_write_through(&mut self, write_through: bool) {
-        self.value.set_bit(3, write_through);
-    }
-    pub fn cache_disable(&self) -> bool {
-        self.value.bit(4)
-    }
-    pub fn set_cache_disable(&mut self, cache_disable: bool) {
-        self.value.set_bit(4, cache_disable);
-    }
-    pub fn accessed(&self) -> bool {
-        self.value.bit(5)
-    }
-    pub fn set_accessed(&mut self, accessed: bool) {
-        self.value.set_bit(5, accessed);
-    }
-    pub fn physical_address(&self) -> usize {
-        self.value.bits(12..=51) as usize
-    }
-    pub fn set_physical_address(&mut self, address: u64) {
-        self.value &= 0xFFF0000000000FFF;
-        self.value |= (address & 0xFFFFFFFFFF) << 12;
-    }
-    pub fn available(&self) -> usize {
-        (self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
-            as usize
     }
 }
-
-pub struct PageMapLevel4 {
-    pub entries: [PageMapLevel4Entry; 512],
-}
-
-pub struct PageMapLevel4Entry {
-    value: u64,
-}
-
-impl PageMapLevel4Entry {
-    pub fn execute_disable(&self) -> bool {
-        self.value.bit(63)
-    }
-    pub fn present(&self) -> bool {
-        self.value.bit(0)
-    }
-    pub fn set_present(&mut self, present: bool) {
-        self.value.set_bit(0, present);
-    }
-    pub fn writable(&self) -> bool {
-        self.value.bit(1)
-    }
-    pub fn set_writable(&mut self, writable: bool) {
-        self.value.set_bit(1, writable);
-    }
-    pub fn user_accessible(&self) -> bool {
-        self.value.bit(2)
-    }
-    pub fn set_user_accessible(&mut self, accessible: bool) {
-        self.value.set_bit(2, accessible);
-    }
-    pub fn write_through(&self) -> bool {
-        self.value.bit(3)
-    }
-    pub fn set_write_through(&mut self, write_through: bool) {
-        self.value.set_bit(3, write_through);
-    }
-    pub fn cache_disable(&self) -> bool {
-        self.value.bit(4)
-    }
-    pub fn set_cache_disable(&mut self, cache_disable: bool) {
-        self.value.set_bit(4, cache_disable);
-    }
-    pub fn accessed(&self) -> bool {
-        self.value.bit(5)
-    }
-    pub fn set_accessed(&mut self, accessed: bool) {
-        self.value.set_bit(5, accessed);
-    }
-    pub fn physical_address(&self) -> usize {
-        self.value.bits(12..=51) as usize
-    }
-    pub fn set_physical_address(&mut self, address: u64) {
-        self.value &= 0xFFF0000000000FFF;
-        self.value |= (address & 0xFFFFFFFFFF) << 12;
-    }
-    pub fn set_pointer_table(&mut self, table: &PageDirectoryPointerTable) {
-        self.set_physical_address(&raw const table as u64);
-    }
-    pub fn available(&self) -> usize {
-        (self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
-            as usize
-    }
-}
-
-pub struct PageDirectoryPointerTable {
-    entries: [*mut PageDirectory; 4],
-}
-
-pub struct PageDirectoryPointer {
-    value: u64,
-}
-
-impl PageDirectoryPointer {
-    pub fn execute_disable(&self) -> bool {
-        self.value.bit(63)
-    }
-    pub fn present(&self) -> bool {
-        self.value.bit(0)
-    }
-    pub fn set_present(&mut self, present: bool) {
-        self.value.set_bit(0, present);
-    }
-    pub fn writable(&self) -> bool {
-        self.value.bit(1)
-    }
-    pub fn set_writable(&mut self, writable: bool) {
-        self.value.set_bit(1, writable);
-    }
-    pub fn user_accessible(&self) -> bool {
-        self.value.bit(2)
-    }
-    pub fn set_user_accessible(&mut self, accessible: bool) {
-        self.value.set_bit(2, accessible);
-    }
-    pub fn write_through(&self) -> bool {
-        self.value.bit(3)
-    }
-    pub fn set_write_through(&mut self, write_through: bool) {
-        self.value.set_bit(3, write_through);
-    }
-    pub fn cache_disable(&self) -> bool {
-        self.value.bit(4)
-    }
-    pub fn set_cache_disable(&mut self, cache_disable: bool) {
-        self.value.set_bit(4, cache_disable);
-    }
-    pub fn accessed(&self) -> bool {
-        self.value.bit(5)
-    }
-    pub fn set_accessed(&mut self, accessed: bool) {
-        self.value.set_bit(5, accessed);
-    }
-    pub fn physical_address(&self) -> *mut PageDirectory {
-        self.value.bits(12..=51) as *mut PageDirectory
-    }
-    pub fn set_physical_address(&mut self, address: u64) {
-        self.value &= 0xFFF0000000000FFF;
-        self.value |= (address & 0xFFFFFFFFFF) << 12;
-    }
-    pub fn set_page_directory(&mut self, dir: &PageDirectory) {
-        self.set_physical_address(&raw const dir as u64);
-    }
-    pub fn available(&self) -> usize {
-        (self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
-            as usize
-    }
-}
-
-pub struct PageDirectory {
-    entries: [PageDirectoryEntry; 512],
-}
-
-pub struct PageDirectoryEntry {
-    value: u64,
-}
-
-impl PageDirectoryEntry {
-    pub fn execute_disable(&self) -> bool {
-        self.value.bit(63)
-    }
-    pub fn present(&self) -> bool {
-        self.value.bit(0)
-    }
-    pub fn set_present(&mut self, present: bool) {
-        self.value.set_bit(0, present);
-    }
-    pub fn writable(&self) -> bool {
-        self.value.bit(1)
-    }
-    pub fn set_writable(&mut self, writable: bool) {
-        self.value.set_bit(1, writable);
-    }
-    pub fn user_accessible(&self) -> bool {
-        self.value.bit(2)
-    }
-    pub fn set_user_accessible(&mut self, accessible: bool) {
-        self.value.set_bit(2, accessible);
-    }
-    pub fn write_through(&self) -> bool {
-        self.value.bit(3)
-    }
-    pub fn set_write_through(&mut self, write_through: bool) {
-        self.value.set_bit(3, write_through);
-    }
-    pub fn cache_disable(&self) -> bool {
-        self.value.bit(4)
-    }
-    pub fn set_cache_disable(&mut self, cache_disable: bool) {
-        self.value.set_bit(4, cache_disable);
-    }
-    pub fn accessed(&self) -> bool {
-        self.value.bit(5)
-    }
-    pub fn set_accessed(&mut self, accessed: bool) {
-        self.value.set_bit(5, accessed);
-    }
-    pub fn physical_address(&self) -> usize {
-        self.value.bits(12..=51) as usize
-    }
-    pub fn set_physical_address(&mut self, address: u64) {
-        self.value &= 0xFFF0000000000FFF;
-        self.value |= (address & 0xFFFFFFFFFF) << 12;
-    }
-    pub fn available(&self) -> usize {
-        (self.value.bits(52..=62) << 4 & self.value.bits(8..=11) << 1 & self.value.bits(6..=6))
-            as usize
-    }
-}
-
-pub use page_table::PageTable;

src/kernel/main.rs

@@ -25,18 +25,16 @@ use arch::x86_64::serial::Serialport;
 
 use boot::{modules::*, params, *};
 use constants::*;
-use intbits::Bits;
 use limine::firmware_type::FirmwareType;
 use log::*;
 use memory::alloc::{format, string::*, vec};
-use memory::{HHDM_RESPONSE, MEMMAP_REQUEST};
+use memory::MEMMAP_REQUEST;
 use params::*;
 
 use limine::memory_map::EntryType;
 #[allow(unused_imports)]
 use lzma_rs::lzma_decompress;
 
-use crate::arch::paging::PageMapLevel4;
 use crate::arch::x86_64::interrupts::IDT;
 
 #[unsafe(no_mangle)]
@@ -201,31 +199,7 @@ unsafe extern "C" fn main() -> ! {
         panic!("Memory map contains no entries");
     }
 
-    log_info!("HHDM offset: 0x{:X}", HHDM_RESPONSE.offset());
+    arch::x86_64::paging::get_mappings();
-
-    log_info!("Paging: {}", arch::asm::read_cr0().bit(31));
-    log_info!("Protection: {}", arch::asm::read_cr0().bit(0));
-    log_info!(
-        "Physical Address Extensions: {}",
-        arch::asm::read_cr4().bit(5)
-    );
-    log_info!("Page Size Extensions: {}", arch::asm::read_cr4().bit(4));
-    log_info!(
-        "Paging mode: {}",
-        match memory::PAGING_REQUEST.get_response().unwrap().mode() {
-            limine::paging::Mode::FOUR_LEVEL => "Four-Level",
-            limine::paging::Mode::FIVE_LEVEL => "Five-Level",
-            _ => unreachable!(),
-        }
-    );
-    log_info!("CR3 Value: 0b{:064b}", arch::asm::read_cr3());
-    // Physical address of Page Map Level 4 Table
-    let pml4_ptr = ((arch::asm::read_cr3().bits(12..=63) << 12) + HHDM_RESPONSE.offset())
-        as *const PageMapLevel4;
-    log_info!("Page Map Level 4 Table Address: 0x{:x}", pml4_ptr.addr());
-    log_info!("Physical address of first entry: {}", unsafe {
-        (*pml4_ptr).entries[0].physical_address()
-    });
 
     panic!("Bailing");
 

src/kernel/process.rs

@@ -1,7 +1,6 @@
 // Copyright (c) 2025 shibedrill
 // SPDX-License-Identifier: GPL-3.0-or-later
 
-use crate::arch::paging::{PageDirectory, PageTable};
 use crate::memory::alloc;
 use alloc::string::String;
 use alloc::vec::Vec;
@@ -28,12 +27,6 @@ pub struct Process {
     stack_length: usize,
     /// The stack pointer, which is relative to the memory region start.
     stack_pointer: usize,
-    /// The page direcory pointing to this process's pages.
-    page_directory: PageDirectory,
-    /// All pages owned by the process.
-    /// When creating a process, we should create one read-write data page,
-    /// with execution disabled, and one read-only executable page.
-    page_tables: Vec<PageTable>,
     /// Process priority. Lower number is higher priority.
     priority: u16,
 }