Only enumerate pages in dev build

Cargo.lock

@@ -61,6 +61,12 @@ version = "1.5.0"
 source = "registry+https://github.com/rust-lang/crates.io-index"
 checksum = "1fd0f2584146f6f2ef48085050886acf353beff7305ebd1ae69500e27c67f64b"
 
+[[package]]
+name = "cfg-if"
+version = "1.0.4"
+source = "registry+https://github.com/rust-lang/crates.io-index"
+checksum = "9330f8b2ff13f34540b44e946ef35111825727b38d33286ef986142615121801"
+
 [[package]]
 name = "core2"
 version = "0.3.3"
@@ -133,6 +139,7 @@ version = "0.3.1"
 dependencies = [
  "acid_alloc",
  "acpi",
+ "cfg-if",
  "enumflags2",
  "fdt",
  "flagset",

Cargo.toml

@@ -7,6 +7,7 @@ license = "MIT"
 [dependencies]
 acid_alloc = { version = "0.1.0", features = ["alloc"] }
 acpi = { version = "6.0.1", optional = true }
+cfg-if = "1.0.4"
 enumflags2 = "0.7.12"
 fdt = { git = "https://github.com/repnop/fdt", version = "0.2.0-alpha1", optional = true }
 flagset = "0.4.7"

src/kernel/arch/x86_64/paging.rs

@@ -3,6 +3,7 @@
 
 #![allow(dead_code)]
 
+use crate::constants::KERNEL_BUILD_PROFILE;
 use crate::{LOGGER, LogLevel, format, log_info, memory::HHDM_RESPONSE};
 use x86_64::{
     PhysAddr, VirtAddr,
@@ -32,8 +33,6 @@ pub fn get_mappings() {
             _ => unreachable!(),
         }
     );
-    let pml4_phys_addr = Cr3::read_raw().0.start_address();
-    log_info!("Page Map Level 4 Address: 0x{:x}", pml4_phys_addr.as_u64());
     log_info!(
         "Page-Level Write-Through: {}",
         Cr3::read().1.contains(Cr3Flags::PAGE_LEVEL_WRITETHROUGH)
@@ -42,10 +41,14 @@ pub fn get_mappings() {
         "Page-Level Cache Disable: {}",
         Cr3::read().1.contains(Cr3Flags::PAGE_LEVEL_CACHE_DISABLE)
     );
-    let pml4: &'static mut PageTable = table_from_phys_addr(pml4_phys_addr);
 
+    if KERNEL_BUILD_PROFILE == "debug" {
+        let pml4_phys_addr = Cr3::read_raw().0.start_address();
+        log_info!("Page Map Level 4 Address: 0x{:x}", pml4_phys_addr.as_u64());
+        let pml4: &'static mut PageTable = table_from_phys_addr(pml4_phys_addr);
         iter_table(pml4, 4);
     }
+}
 
 fn table_from_phys_addr(address: PhysAddr) -> &'static mut PageTable {
     let virt_addr: VirtAddr = VirtAddr::new(address.as_u64() + HHDM_RESPONSE.offset());

src/kernel/arch/x86_64/serial.rs

@@ -144,7 +144,8 @@ impl SerialPort {
 
     /// Get whether the transmit buffer is empty.
     pub fn is_transmit_empty(&mut self) -> bool {
-        self.get_line_status().contains(LineStatus::TransmitterEmpty)
+        self.get_line_status()
+            .contains(LineStatus::TransmitterEmpty)
     }
 
     fn block_until_transmit_empty(&mut self) {